processor 6502
;
;
;Register names and descriptions from Contiki/uIP driver source
;See http://www.sics.se/~adam/uip/ or http://ide64.come.to for the original
;
;
;
;
;
;
;EQUATES=============================================================
ETHBASE	   = $de10
ETHBSR 	   = ETHBASE+$0e  ;Bank select register             R/W (2B)

;Register bank 0 
ETHTCR 	   = ETHBASE       ;Transmition control register     R/W (2B)
ETHEPHSR   = ETHBASE+2     ;EPH status register              R/O (2B)
ETHRCR     = ETHBASE+4     ;Receive control register         R/W (2B)
ETHECR     = ETHBASE+6     ;Counter register                 R/O (2B)
ETHMIR     = ETHBASE+8     ;Memory information register      R/O (2B)
ETHMCR     = ETHBASE+$0a   ;Memory Config. reg.    +0 R/W +1 R/O (2B)

;Register bank 1 
ETHCR      = ETHBASE       ;Configuration register           R/W (2B)
ETHBAR     = ETHBASE+2     ;Base address register            R/W (2B)
ETHIAR     = ETHBASE+4     ;Individual address register      R/W (6B)
ETHGPR     = ETHBASE+$0a   ;General address register         R/W (2B)
ETHCTR     = ETHBASE+$0c   ;Control register                 R/W (2B)

;Register bank 2 
ETHMMUCR   = ETHBASE       ;MMU command register             W/O (1B)
ETHAUTOTX  = ETHBASE+1     ;AUTO TX start register           R/W (1B)
ETHPNR     = ETHBASE+2     ;Packet number register           R/W (1B)
ETHARR     = ETHBASE+3     ;Allocation result register       R/O (1B)
ETHFIFO    = ETHBASE+4     ;FIFO ports register              R/O (2B)
ETHPTR     = ETHBASE+6     ;Pointer register                 R/W (2B)
ETHDATA    = ETHBASE+8     ;Data register                    R/W (4B)
ETHIST     = ETHBASE+$0c   ;Interrupt status register        R/O (1B)
ETHACK     = ETHBASE+$0c   ;Interrupt acknowledge register   W/O (1B)
ETHMSK     = ETHBASE+$0d   ;Interrupt mask register          R/W (1B)

;Register bank 3 
ETHMT      = ETHBASE       ;Multicast table                  R/W (8B)
ETHMGMT    = ETHBASE+8     ;Management interface             R/W (2B)
ETHREV     = ETHBASE+$0a   ;Revision register                R/W (2B)
ETHERCV    = ETHBASE+$0c   ;Early RCV register               R/W (2B)

;ZERO PAGE LOCATIONS
INPTR = $57
;====================================================================
;
;
	org $0801
BASIC
	dc.b $0c, $08, $06, $00,$9e, $20, $32, $30
	dc.b $36, $34, $00, $00,$00, $00, $00

MAIN
	jsr lan91c96_init
MAIN1
	jsr lan91c96_poll
	jmp MAIN1


lan91c96_init:
; Check if high byte is $33 
	lda ETHBSR+1
	cmp #$33
	beq lan91c96_init1
	rts;Error
lan91c96_init1:
;Select Bank 0
	lda #$00
	sta ETHBSR
; Reset ETH card 
	lda #%10000000             ;Software reset
	sta ETHRCR+1
	lda #0
	sta ETHRCR
	sta ETHRCR+1
; delay 
	ldx #0
lan91c96_init2:
	cmp ($ff,x)                ;6 cycles
	cmp ($ff,x)                ;6 cycles
	dex                        ;2 cycles
	bne lan91c96_init2         ;3 cycles
	                           ;17*256=4352 => 4,4 ms
; Enable transmit and receive 
	lda #%10000001             ;Enable transmit TXENA, PAD_EN
	sta ETHTCR
	lda #%00000010	 	   ;promisc mode
	sta ETHRCR
	lda #%00000011        	   ;Enable receive, strip CRC ???
	sta ETHRCR+1
	lda ETHCR+1
	ora #%00010000             ;No wait (IOCHRDY)
	sta ETHCR+1
	lda #%00001001             ;Auto release
	sta ETHCTR+1
;Select Bank 1
	lda #$01
	sta ETHBSR
; Set MAC address 
	lda MY_MAC_ADDR
	sta ETHIAR
	lda MY_MAC_ADDR+1
	sta ETHIAR+1
	lda MY_MAC_ADDR+2
	sta ETHIAR+2
	lda MY_MAC_ADDR+3
	sta ETHIAR+3
	lda MY_MAC_ADDR+4
	sta ETHIAR+4
	lda MY_MAC_ADDR+5
	sta ETHIAR+5
	lda #%00001111               ;RCV INT, ALLOC INT, TX INT, TX EMPTY
	sta ETHMSK
	rts

;POLL FOR PACKET==============================================================
lan91c96_poll:
;Select Bank 2
	lda #$02
	sta ETHBSR
	lda ETHIST
	sta $0400
	and #%00000001                ;RCV INT
	bne lan91c96_poll1
;No packet available 
	rts
;packet available, put it in INPACKET
lan91c96_poll1
	inc IN_PACKET_COUNT
	bne lp0
	inc IN_PACKET_COUNT+$01
lp0
	lda #0
	sta ETHPTR
	lda #%11100000               ;RCV,AUTO INCR.,READ
	sta ETHPTR+1
	lda ETHDATA               ;Status word
	lda ETHDATA
	sta IN_PACKET_STATUS            ;High byte only
	lda ETHDATA               ;Total number of bytes
	sta IN_PACKET_LENGTH
	lda ETHDATA
	sta IN_PACKET_LENGTH+1
; Last word contain 'last data byte' and $60 
; or 'fill byte' and $40 
	clc
	lda IN_PACKET_LENGTH+1
	sbc #$06
	bcc lan91c96_poll2
	dec IN_PACKET_LENGTH
lan91c96_poll2
;The packet contains 3 extra words
;packet_length -= 6
	lda IN_PACKET_STATUS
	and #$10
	beq lan91c96_poll3
	inc IN_PACKET_LENGTH+1
	bne lan91c96_poll3
	inc IN_PACKET_LENGTH
lan91c96_poll3
;Set zero-page pointer to our incoming packet area.
  	lda #<INPACKET
  	sta INPTR
  	lda #>INPACKET
  	sta INPTR+1
;Read in packet to our incoming packet buffer
  	ldy #0
  	ldx IN_PACKET_LENGTH+1
  	beq lan91c96_poll4      ;packet_length < 256
lan91c96_poll5
  	lda ETHDATA
  	sta (INPTR),y
  	iny
  	bne lan91c96_poll5
  	inc INPTR+1
  	dex
  	bne lan91c96_poll5
lan91c96_poll4
  	lda ETHDATA
  	sta (INPTR),y
  	iny
  	cpy IN_PACKET_LENGTH
  	bne lan91c96_poll4
;Remove and release RX packet from FIFO
	lda #%10000000
  	sta ETHMMUCR

	rts

;DATA=========================================================================
;
;
MY_MAC_ADDR	dc.b $0b,$0c,$0f,$0f,$0c,$0b

IN_PACKET_COUNT		dc.w $0000,$0000
IN_PACKET_STATUS	dc.b $00
IN_PACKET_LENGTH	dc.w $0000
INPACKET	equ $0400