processor 6502
;
;
;Register names and descriptions from Contiki/uIP driver source
;See http://www.sics.se/~adam/uip/ or http://ide64.come.to for the original
;
;EQUATES=============================================================
ETHBASE	   = $de10
ETHBSR 	   = ETHBASE+$0e  ;Bank select register             R/W (2B)

;Register bank 0 
ETHTCR 	   = ETHBASE       ;Transmition control register     R/W (2B)
ETHEPHSR   = ETHBASE+2     ;EPH status register              R/O (2B)
ETHRCR     = ETHBASE+4     ;Receive control register         R/W (2B)
ETHECR     = ETHBASE+6     ;Counter register                 R/O (2B)
ETHMIR     = ETHBASE+8     ;Memory information register      R/O (2B)
ETHMCR     = ETHBASE+$0a   ;Memory Config. reg.    +0 R/W +1 R/O (2B)

;Register bank 1 
ETHCR      = ETHBASE       ;Configuration register           R/W (2B)
ETHBAR     = ETHBASE+2     ;Base address register            R/W (2B)
ETHIAR     = ETHBASE+4     ;Individual address register      R/W (6B)
ETHGPR     = ETHBASE+$0a   ;General address register         R/W (2B)
ETHCTR     = ETHBASE+$0c   ;Control register                 R/W (2B)

;Register bank 2 
ETHMMUCR   = ETHBASE       ;MMU command register             W/O (1B)
ETHAUTOTX  = ETHBASE+1     ;AUTO TX start register           R/W (1B)
ETHPNR     = ETHBASE+2     ;Packet number register           R/W (1B)
ETHARR     = ETHBASE+3     ;Allocation result register       R/O (1B)
ETHFIFO    = ETHBASE+4     ;FIFO ports register              R/O (2B)
ETHPTR     = ETHBASE+6     ;Pointer register                 R/W (2B)
ETHDATA    = ETHBASE+8     ;Data register                    R/W (4B)
ETHIST     = ETHBASE+$0c   ;Interrupt status register        R/O (1B)
ETHACK     = ETHBASE+$0c   ;Interrupt acknowledge register   W/O (1B)
ETHMSK     = ETHBASE+$0d   ;Interrupt mask register          R/W (1B)

;Register bank 3 
ETHMT      = ETHBASE       ;Multicast table                  R/W (8B)
ETHMGMT    = ETHBASE+8     ;Management interface             R/W (2B)
ETHREV     = ETHBASE+$0a   ;Revision register                R/W (2B)
ETHERCV    = ETHBASE+$0c   ;Early RCV register               R/W (2B)

;ZERO PAGE LOCATIONS
INPTR = $57
;====================================================================
;
;
	org $0801
BASIC
	dc.b $0c, $08, $06, $00,$9e, $20, $32, $30
	dc.b $36, $34, $00, $00,$00, $00, $00

MAIN
	jsr lan91c96_init
MAIN1
	jsr lan91c96_send
	rts

lan91c96_init:
; Check if high byte is $33 
	lda ETHBSR+1
	cmp #$33
	beq lan91c96_init1
	rts;Error
lan91c96_init1:
;Select Bank 0
	lda #$00
	sta ETHBSR
; Reset ETH card 
	lda #%10000000             ;Software reset
	sta ETHRCR+1
	lda #0
	sta ETHRCR
	sta ETHRCR+1
; delay 
	ldx #0
lan91c96_init2:
	cmp ($ff,x)                ;6 cycles
	cmp ($ff,x)                ;6 cycles
	dex                        ;2 cycles
	bne lan91c96_init2         ;3 cycles
	                           ;17*256=4352 => 4,4 ms
; Enable transmit and receive 
	lda #%10000001             ;Enable transmit TXENA, PAD_EN
	sta ETHTCR
	lda #%00000010	 	   ;promisc mode
	sta ETHRCR
	lda #%00000011        	   ;Enable receive, strip CRC ???
	sta ETHRCR+1
	lda ETHCR+1
	ora #%00010000             ;No wait (IOCHRDY)
	sta ETHCR+1
	lda #%00001001             ;Auto release
	sta ETHCTR+1
;Select Bank 1
	lda #$01
	sta ETHBSR
; Set MAC address 
	lda MY_MAC_ADDR
	sta ETHIAR
	lda MY_MAC_ADDR+1
	sta ETHIAR+1
	lda MY_MAC_ADDR+2
	sta ETHIAR+2
	lda MY_MAC_ADDR+3
	sta ETHIAR+3
	lda MY_MAC_ADDR+4
	sta ETHIAR+4
	lda MY_MAC_ADDR+5
	sta ETHIAR+5
	lda #%00001111               ;RCV INT, ALLOC INT, TX INT, TX EMPTY
	sta ETHMSK
	rts
;=============================================================================
lan91c96_send
;bank 2
	lda #$02
	sta ETHBSR
;only allocate one block
	lda #$00
	ora #%00100000        ;Command 0010: Allocate Memory for TX
  	sta ETHMMUCR

;Wait for up to 200us
	ldx #8                 
lan91c96_send3                   
	lda ETHIST
  	and #%00001000        ;Check ALLOC_INT on status register
  	bne lan91c96_send4
  	dex
  	bne lan91c96_send3
	rts		      ;Choked, return (error?)
	
lan91c96_send4
;Acknowledge int.
	lda #%00001000        
  	sta ETHACK

  	lda ETHARR	      ;Get address from Allocation Result Register
  	sta ETHPNR	      ;And use it to set our packet address

  	lda #0
  	sta ETHPTR
  	lda #%01000000        ;AUTO INCR.
  	sta ETHPTR+1

  	lda #0                ;Status written by CSMA
 	sta ETHDATA
  	sta ETHDATA
;Packet size is $2a + overhead (6 bytes) = $30
	lda #$30 	      ;packet length lo-byte
 	sta ETHDATA
  	lda #$00 	      ;packet length hi-byte
  	sta ETHDATA

;Write actual packet to Transmit 
	ldx #$00	
lan91c96_sendloop
	lda OUTPACKET,x
	sta ETHDATA
	inx
	cpx #$2a
	bne lan91c96_sendloop
  	lda #%00100000
  	sta ETHDATA        ;Control byte
  	lda #%11000000        ;ENQUEUE PACKET - transmit packet
  	sta ETHMMUCR
	rts

;DATA=========================================================================
;
;
MY_MAC_ADDR	dc.b $0b,$0c,$0f,$0f,$0c,$0b

;ARP "Who has 192.168.0.2 tell 192.168.0.64"
OUTPACKET 
	dc.b $ff,$ff,$ff,$ff,$ff,$ff ;$00-$05: Dest MAC  
	dc.b $0b,$0c,$0f,$0f,$0c,$0b ;$06-$0b: Source MAC
	dc.b $08,$06                 ;$0c-$0d: Packet Type
	dc.b $00,$01                 ;$0e-$0f: Hardware MAC Address Type
	dc.b $08,$00                 ;$10-$11: Protocol Address Type
	dc.b $06                     ;$12    : Hardware MAC Address Size
	dc.b $04                     ;$13    : Protocol Address Size
	dc.b $00,$01                 ;$14-$15: Opcode
	dc.b $0b,$0c,$0f,$0f,$0c,$0b ;$16-$1b: Sender MAC Address
	dc.b $c0,$a8,$00,$40         ;$1c-$1f: Sender IP Address
	dc.b $00,$00,$00,$00,$00,$00 ;$20-$25: Target MAC Address
	dc.b $c0,$a8,$00,$02         ;$26-$29: Target IP Address